Statistical Timing Analysis of Asynchronous Circuits Using Logic Simulator

The lack of methods and tools for performance estimations in asynchronous circuits is one of the main reasons why this design methodology, beside its advantages, is still unpopular among designers. Using a logic simulator it is possible to efficiently estimate all worst-case path delays in one asynchronous circuit, which can be crucial for overcoming this problem. This paper describes a method for statistical estimation of topological delays in asynchronous circuits, based on the application of a VHDL simulator. The method is verified on a set of chosen asynchronous circuits and in compare with other similar methods shows higher efficiency.